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rev.2.00, may.26.2004, page 1 of 16 r1lv0416c-i series wide temperature range version 4m sram (256-kword 16-bit) rej03c0105-0200z rev. 2.00 may.26.2004 description the r1lv0416c-i is a 4-mbit static ram organized 256-kword 16-bit. r1lv0416c-i series has realized higher density, higher performance and low power consumption by employing cmos process technology (6-transistor memory cell). the r1lv0416c-i series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. it has packaged in 44-pin tsop ii. features ? single 2.5 v and 3.0 v supply: 2.2 v to 3.6 v ? fast access time: 55/70 ns (max) ? power dissipation: ? active: 5.0 mw/mhz (typ)(v cc = 2.5 v) : 6.0 mw/mhz (typ) (v cc = 3.0 v) ? standby: 1.25 w (typ) (v cc = 2.5 v) : 1.5 w (typ) (v cc = 3.0 v) ? completely static memory. ? no clock or timing strobe required ? equal access and cycle times ? common data input and output. ? three state output ? battery backup operation. ? 2 chip selection for battery backup ? temperature range: ? 40 to +85 c
r1lv0416c-i series rev.2.00, may.26.2004, page 2 of 16 ordering information type no. access time package r1lv0416csb-5si 55 ns 400-mil 44-pin plastic tsop ii (44p3w-h) R1LV0416CSB-7LI 70 ns
r1lv0416c-i series rev.2.00, may.26.2004, page 3 of 16 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1# i/o0 i/o1 i/o2 i/o3 v v i/o4 i/o5 i/o6 i/o7 we# a17 a16 a15 a14 a13 cc ss a5 a6 a7 oe# ub# lb# i/o15 i/o14 i/o13 i/o12 v v i/o11 i/o10 i/o9 i/o8 cs2 a8 a9 a10 a11 a12 cc ss (top view) 44-pin tsop pin description pin name function a0 to a17 address input i/o0 to i/o15 data input/output cs1# ( cs1 ) chip select 1 cs2 chip select 2 oe# ( oe ) output enable we# ( we ) write enable lb# ( lb ) lower byte select ub# ( ub ) upper byte select v cc power supply v ss ground
r1lv0416c-i series rev.2.00, may.26.2004, page 4 of 16 block diagram ? i/o0 i/o15 cs2 we# oe# a4 a3 a2 a5 a0 v v cc ss row decoder memory matrix 2,048 x 2,048 column i/o column decoder input data control control logic a6 a12 a11 a10 a9 a8 a13 a14 a15 a16 a17 a7 cs1# lb# ub# a1 lsb msb lsb msb
r1lv0416c-i series rev.2.00, may.26.2004, page 5 of 16 operation table cs1# cs2 we# oe# ub# lb# i/o0 to i/o7 i/o8 to i/o15 operation h high-z high-z standby l high-z high-z standby h h high-z high-z standby l h h l l l dout dout read l h h l h l dout high-z lower byte read l h h l l h high-z dout upper byte read l h l l l din din write l h l h l din high-z lower byte write l h l l h high-z din upper byte write l h h h high-z high-z output disable note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ? 0.5 to +4.6 v terminal voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0.3 * 2 v power dissipation p t 0.7 w operating temperature topr ? 40 to +85 c storage temperature range tstg ? 65 to +150 c storage temperature range under bias tbias ? 40 to +85 c notes: 1. v t min: ? 3.0 v for pulse half-width 30 ns. 2. maximum voltage is +4.6 v. dc operating conditions (ta = ? 40 to +85 c) parameter symbol min typ max unit note supply voltage v cc 2.2 2.5/3.0 3.6 v v ss 0 0 0 v input high voltage v cc = 2.2 v to 2.7 v v ih 2.0 ? v cc + 0.3 v v cc = 2.7 v to 3.6 v v ih 2.2 ? v cc + 0.3 v input low voltage v cc = 2.2 v to 2.7 v v il ? 0.2 ? 0.4 v 1 v cc = 2.7 v to 3.6 v v il ? 0.3 ? 0.6 v 1 note: 1. v il min: ? 3.0 v for pulse half-width 30 ns.
r1lv0416c-i series rev.2.00, may.26.2004, page 6 of 16 dc characteristics parameter symbol min typ max unit test conditions input leakage current |i li | ? ? 1 a vin = v ss to v cc output leakage current |i lo | ? ? 1 a cs1# = v ih or cs2 = v il or oe# = v ih or we# = v il or lb# = ub# = v ih , v i/o = v ss to v cc operating current i cc ? 5 * 1 20 ma cs1# = v il , cs2 = v ih , others = v ih /v il , i i/o = 0 ma average operating current i cc1 ? 8 * 1 25 ma min. cycle, duty = 100%, i i/o = 0 ma, cs1# = v il , cs2 = v ih , others = v ih /v il i cc2 ? 2 * 1 5 ma cycle time = 1 s, duty = 100%, i i/o = 0 ma, cs1# 0.2 v, cs2 v cc ? 0.2 v v ih v cc ? 0.2 v, v il 0.2 v standby current i sb ? 0.1 * 1 0.3 ma cs2 = v il to +85 c i sb1 ? ? 10 a vin 0 v to +70 c i sb1 ? ? 8 a (1) 0 v cs2 0.2 v or to +40 c i sb1 ? 0.7 * 2 3 a (2) cs1# v cc ? 0.2 v, ? 5si to +25 c i sb1 ? 0.5 * 1 3 a cs2 v cc ? 0.2 v or to +85 c i sb1 ? ? 20 a (3) lb# = ub# v cc ? 0.2 v, to +70 c i sb1 ? ? 16 a cs2 v cc ? 0.2 v, to +40 c i sb1 ? 0.7 * 2 10 a cs1# 0.2 v standby current ? 7li to +25 c i sb1 ? 0.5 * 1 10 a output high voltage v cc =2.2 v to 2.7 v v oh 2.0 ? ? v i oh = ? 0.5 ma v cc =2.7 v to 3.6 v v oh 2.4 ? ? v i oh = ? 1 ma v cc =2.2 v to 3.6 v v oh2 v cc ? 0. 2 ? ? v i oh = ? 100 a output low voltage v cc =2.2 v to 2.7 v v ol ? ? 0.4 v i ol = 0.5 ma v cc =2.7 v to 3.6 v v ol ? ? 0.4 v i ol = 2 ma v cc =2.2 v to 3.6 v v ol2 ? ? 0.2 v i ol = 100 a notes: 1. typical values are at v cc = 3.0 v, ta = +25 c and specified loadi ng, and not guaranteed. 2. typical values are at v cc = 3.0 v, ta = +40 c and specified loadi ng, and not guaranteed.
r1lv0416c-i series rev.2.00, may.26.2004, page 7 of 16 capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions note input capacitance cin ? ? 8 pf vin = 0 v 1 input/output capacitance c i/o ? ? 10 pf v i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested. ac characteristics (ta = ? 40 to +85 c, v cc = 2.2 v to 3.6 v, unless otherwise noted.) test conditions ? input pulse levels: v il = 0.4 v, v ih = 2.2 v (v cc = 2.2 v to 2.7 v) : v il = 0.4 v, v ih = 2.4 v (v cc = 2.7 v to 3.6 v) ? input rise and fall time: 5 ns ? input/output timing reference levels: 1.1 v (v cc = 2.2 v to 2.7 v) : 1.4 v (v cc = 2.7 v to 3.6 v) ? output load: see figures (including scope and jig) dout 30pf r1 v tm v tm = 2.3 v r2 r1 = 3070 ? r2 = 3150 ? 50pf dout rl=500 ? 1.4 v output load (a) (v cc = 2.2 v to 2.7 v) output load (b) (v cc = 2.7 v to 3.6 v)
r1lv0416c-i series rev.2.00, may.26.2004, page 8 of 16 read cycle r1lv0416c-i -5si -7li parameter symbol min max min max unit notes read cycle time t rc 55 ? 70 ? ns address access time t aa ? 55 ? 70 ns chip select access time t acs1 ? 55 ? 70 ns t acs2 ? 55 ? 70 ns output enable to output valid t oe ? 35 ? 40 ns output hold from address change t oh 10 ? 10 ? ns lb#, ub# access time t ba ? 55 ? 70 ns chip select to output in low-z t clz1 10 ? 10 ? ns 2, 3 t clz2 10 ? 10 ? ns 2, 3 lb#, ub# disable to low-z t blz 5 ? 5 ? ns 2, 3 output enable to output in low-z t olz 5 ? 5 ? ns 2, 3 chip deselect to output in high-z t chz1 0 20 0 25 ns 1, 2, 3 t chz2 0 20 0 25 ns 1, 2, 3 lb#, ub# disable to high-z t bhz 0 20 0 25 ns 1, 2, 3 output disable to output in high-z t ohz 0 20 0 25 ns 1, 2, 3
r1lv0416c-i series rev.2.00, may.26.2004, page 9 of 16 write cycle r1lv0416c-i -5si -7li parameter symbol min max min max unit notes write cycle time t wc 55 ? 70 ? ns address valid to end of write t aw 50 ? 60 ? ns chip selection to end of write t cw 50 ? 60 ? ns 5 write pulse width t wp 40 ? 50 ? ns 4 lb#, ub# valid to end of write t bw 50 ? 55 ? ns address setup time t as 0 ? 0 ? ns 6 write recovery time t wr 0 ? 0 ? ns 7 data to write time overlap t dw 25 ? 30 ? ns data hold from write time t dh 0 ? 0 ? ns output active from end of write t ow 5 ? 5 ? ns 2 output disable to output in high-z t ohz 0 20 0 25 ns 1, 2, 3 write to output in high-z t whz 0 20 0 25 ns 1, 2 notes: 1. t chz , t ohz , t whz and t bhz are defined as the time at whic h the outputs achieve the open circuit conditions and are not referr ed to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temper ature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occures during the overlap of a low cs1#, a high cs2, a low we# and a low lb# or a low ub#. a write begins at the latest transit ion among cs1# going low, cs2 going high, we# going low and lb# going low or ub# going low. a wr ite ends at the earliest transition among cs1# going high, cs2 going low, we# going high and lb# going high or ub# going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1# going low or cs2 going high to the end of write. 6. t as is measured from the address va lid to the beginning of write. 7. t wr is measured from the earliest of cs1# or we# going high or cs2 going low to the end of write cycle.
r1lv0416c-i series rev.2.00, may.26.2004, page 10 of 16 timing waveform read timing waveform (we# = v ih ) t aa t acs1 t acs2 t clz2 t clz1 t blz t ba t oh t rc valid data address dout valid address high impedance cs1# cs2 lb#, ub# oe# * 1, 2, 3 * 1, 2, 3 * 2, 3 * 2, 3 * 2, 3 * 1, 2, 3 t olz * 2, 3 * 1, 2, 3 t oe t chz1 t chz2 t bhz t ohz
r1lv0416c-i series rev.2.00, may.26.2004, page 11 of 16 write timing waveform (1) (we# clock) address we# t wc t aw t wp * 4 t wr * 7 t cw * 5 t cw * 5 t bw t as * 6 t ow * 2 t whz * 1, 2 t dw t dh valid address valid data cs1# lb#, ub# dout din high impedance cs2
r1lv0416c-i series rev.2.00, may.26.2004, page 12 of 16 write timing waveform (2) (cs# clock, oe# = v ih ) address we# t wc t aw t wp * 4 t wr * 7 t cw * 5 t cw * 5 t bw t as * 6 t dw t dh valid address valid data lb#, ub# dout din high impedance cs2 cs1#
r1lv0416c-i series rev.2.00, may.26.2004, page 13 of 16 write timing waveform (3) (lb#, ub# clock, oe# = v ih ) address we# t wc t aw t wp * 4 t cw * 5 t cw * 5 t bw t wr * 7 t dw t dh valid address valid data lb#, ub# dout din high impedance cs2 cs1# t as * 6
r1lv0416c-i series rev.2.00, may.26.2004, page 14 of 16 low v cc data retention characteristics (ta = ? 40 to +85 c) parameter symbol min typ max unit test conditions * 3 v cc for data retention v dr 2.0 ? ? v vin 0v (1) 0 v cs2 0.2 v or (2) cs2 v cc ? 0.2 v, cs1# v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v to +85 c i ccdr ? ? 10 a to +70 c i ccdr ? ? 8 a to +40 c i ccdr ? 0.7 * 2 3 a ? 5si to +25 c i ccdr ? 0.5 * 1 3 a to +85 c i ccdr ? ? 20 a to +70 c i ccdr ? ? 16 a to +40 c i ccdr ? 0.7 * 2 10 a v cc = 3.0 v, vin 0v (1) 0 v cs2 0.2 v or (2) cs2 v cc ? 0.2 v, cs1# v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v data retention current ? 7li to +25 c i ccdr ? 0.5 * 1 10 a chip deselect to data retention time t cdr 0 ? ? ns see retention waveform operation recovery time t r t rc * 4 ? ? ns notes: 1. typical values are at v cc = 3.0 v, ta = +25 c and specified loadi ng, and not guaranteed. 2. typical values are at v cc = 3.0 v, ta = +40 c and specified loadi ng, and not guaranteed. 3. cs2 controls address buffer, we# buffer, cs1# buffer, oe# buffer, lb#, ub# buffer and din buffer. if cs2 controls data ret ention mode, vin levels (address, we#, oe#, cs1#, lb#, ub#, i/o) can be in the high impedance state. if cs1# controls data retenti on mode, cs2 must be cs2 v cc ? 0.2 v or 0 v cs2 0.2 v. the other input levels (address, we#, oe#, lb#, ub#, i/o) can be in the high impedance state. 4. t rc = read cycle time.
r1lv0416c-i series rev.2.00, may.26.2004, page 15 of 16 low v cc data retention timing waveform (1) (cs1# controlled) ( v cc = 2.2 v to 2.7 v) cc v 2.2 v 2.0 v 0 v cs1# t cdr t r cs1# v ? 0.2 v cc dr v data retention mode low v cc data retention timing waveform (2) (cs1# controlled) ( v cc = 2.7 v to 3.6 v) cc v 2.2 v 2.7 v 0 v cs1# t cdr t r cs1# v ? 0.2 v cc dr v data retention mode low v cc data retention timing waveform (3) (cs2 controlled) ( v cc = 2.2 v to 2.7 v) cc v 2.2 v 0.4 v 0 v cs2 cdr t r 0 v cs2 0.2 v dr v data retention mode t < <
r1lv0416c-i series rev.2.00, may.26.2004, page 16 of 16 low v cc data retention timing waveform (4) (cs2 controlled) ( v cc = 2.7 v to 3.6 v) cc v 2.7 v 0.6 v 0 v cs2 cdr t r 0 v cs2 0.2 v dr v data retention mode t < < low v cc data retention timing waveform (5) (lb#, ub# controlled) ( v cc = 2.2 v to 2.7 v) cc v 2.2 v 2.0 v 0 v lb#, ub# t cdr t r lb#, ub# v ? 0.2 v cc dr v data retention mode low v cc data retention timing waveform (6) (lb#, ub# controlled) ( v cc = 2.7 v to 3.6 v) cc v 2.2 v 2.7 v 0 v lb#, ub# t cdr t r lb#, ub# v ? 0.2 v cc dr v data retention mode
revision history r1lv0416c-i series data sheet contents of modification rev. date page description 1.00 aug.05.2003 ? initial issue 2.00 may.26.2004 5 6 7 8 9 14 absolute maximum ratings notes 2 : +7.0 v to +4.6 v dc characteristics ? 5si and ? 7li items? description are divided. ac characteristics read cycle/notes: t clz1 /t clz2 /t blz /t olz : addition of [2, 3] t chz1 /t chz2 /t bhz /t ohz : addition of [1, 2, 3] write cycle/notes: t ohz : addition of [1, 2, 3] low v cc data retention characteristics ? 5si and ? 7li items? description are divided.
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